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MRF49XA
3.4.2
AUTO CRYSTAL OSCILLATOR
The PLL circuit automatically performs the fine
When an interrupt occurs, irrespective of the OSCEN bit
setting, the crystal oscillator automatically turns on to
supply a clock signal to the microcontroller. After clearing
all interrupts and reading the STSREG, the crystal
oscillator is automatically turned off. The clock tail feature
provides enough clock pulses for the microcontroller to
enter the Low-Power mode. Due to this automatic
feature, it is not possible to turn off the crystal by clearing
the OSCEN bit if any interrupt is active. For example,
after power-on, the POR interrupt must be cleared by
reading STSREG and then writing ‘ 0 ’ to the OSCEN bit
puts the part in Sleep mode. It is necessary to clear all
interrupts before turning the OSCEN bit off as the extra
current required for running the crystal oscillator can
shorten the battery life significantly.
adjustment of carrier frequency. This way, the receiver
can minimize the offset between a transmit and receive
frequency. The frequency control function can be
enabled or disabled through AFCCREG. The range of
offset can be programmed and the offset value is
calculated and added to the frequency control word
within the PLL to incrementally change the carrier
frequency. The MRF49XA can be programmed to
automatically change and control the carrier frequency.
The carrier frequency can also be manually activated
by a strobe signal.
The oscillator provides the reference signal to the RF
synthesizer to set up the transmit or receive frequency.
The crystal oscillator also provides a reference signal to
the RF, baseband circuits and microcontroller interface.
On disabling the clock output (CLKOEN = 1 ), both the
clock tail and auto crystal oscillator usage features are
The PLL
following:
Configuration
register
configures
the
turned off. Only the OSCEN bit controls the crystal
oscillator (considering that both RXCEN and TXCEN
bits are cleared); the interrupts have no effect on it.
The registers associated with the crystal oscillator and
clock are:
? STSREG (see Register 2-1 )
? AFCCREG (see Register 2-3 )
? PMCREG (see Register 2-13 )
? BCSREG (see Register 2-16 )
? Output clock buffer slew rate
? Crystal start-up time
? Phase detector delay
? PLL dithering
? PLL bandwidth
The dithering reduces the noise error when calculating
the fractional-N synthesizer code. When the PLLDD bit
(PLLCREG<2>) is cleared, dithering is enabled and the
settling time is slightly increased. The PLL bandwidth
?
PLLCREG (see Register 2-17 )
can accommodate higher data rates above 90 kbps.
The reduced PLL bandwidth allows faster settling time
3.5 Phase-Locked Loop
The synthesizer consists of a PLL, oscillator and VCO
for controlling the channel frequency. The synthesizer
must be enabled when either the transmitter or the
receiver is enabled. For faster RX/TX switching, the
and reduced phase noise, and thus, results in a better
RX performance. See Register 2-17 for details on PLL
setting and configuration.
The registers associated with the PLL are:
? STSREG (see Register 2-1 )
synthesizer block must be kept on. Enabling the
transmitter using the TXCEN bit (PMCREG<5>) will
turn on the PA, and since the synthesizer is already up
and running, the PA immediately produces the TX
signal at the output. The oscillator must also be
enabled to provide the reference frequency for the PLL.
On power-up, the synthesizer performs the calibration
automatically. The synthesizer also has an internal
start-up calibration procedure. If there are significant
changes in voltage or temperature, recalibration should
be performed by simply disabling the synthesizer and
re-enabling it. When set, the SYNEN bit
(PMCREG<4>) enables the synthesizer.
?
?
?
?
AFCCREG (see Register 2-3 )
PMCREG (see Register 2-13 )
BCSREG (see Register 2-16 )
PLLCREG (see Register 2-17 )
DS70590C-page 48
Preliminary
? 2009-2011 Microchip Technology Inc.
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